1. Field of the Invention
The present invention relates generally to voltage-controlled oscillation circuits (hereinafter referred to as VCO). More particularly, the invention relates to a voltage-controlled oscillation circuit the oscillation frequency of which changes in response to an externally applied control voltage.
2. Description of the Background Art
FIG. 1 is a circuit diagram showing one example of a conventional VCO. In FIG. 1, VCO 1 includes an oscillation stage 2, a buffer stage 3, and an output matching stage 4. Oscillation stage 2 has its oscillation frequency changed in response to a control voltage applied to its control terminal C. Buffer stage 3 prevents the oscillation frequency at oscillation stage 2 from being changed due to load fluctuations. Output matching stage 4 performs matching with a succeeding stage circuit connected to an output terminal P and suppresses harmonics. Oscillation stage 2 includes a resonance circuit 21. Resonance circuit 21 includes a choke coil L3, a varactor diode VD for changing the resonance frequency of the resonance circuit 21, a coupling capacitor C9, and a resonance inductor L2, and a control voltage is applied from control terminal C through choke coil L3 to the cathode of varactor diode VD and one end of coupling capacitor C9. Varactor diode VD has its anode grounded, while the other end of coupling capacitor C9 is connected to one end of resonance inductor L2 and one end of a coupling capacitor C8. The other end of resonance inductor L2 is grounded.
Oscillation stage 2 includes an oscillation transistor Q2 having a base connected to the other end of capacitor C8. The base of oscillation transistor Q2 is also provided as a bias voltage with a voltage produced by voltage dividing by bias resistors R1, R2, and R3 connected in series between a power supply terminal B and ground. A capacitor C6 is connected between the base and emitter of oscillation transistor Q2, while a resistor R4 and a capacitor C7 are connected in parallel between the emitter of oscillation transistor Q2 and ground. Capacitors C6 and C7 constitute a Colpitts capacitance, and oscillation transistor Q2 together with capacitors C6, C7 and resonance inductor L2 constitute a Colpitts oscillator and oscillates according to a frequency at which resonance occurs in resonance circuit 21.
The oscillation output of oscillation stage 2 is applied to buffer stage 3 through coupling capacitor C5. Buffer stage 3 includes a buffer transistor Q1 having its base provided with the oscillation output of oscillation stage 2, and a high frequency bypass capacitor C4 connected between the emitter of buffer transistor Q1 and ground, and the emitter of buffer transistor Q1 is also connected to the collector of oscillation transistor Q2. Buffer transistor Q1 receives at its base the oscillation output of oscillation stage 2, and outputs the same from its collector for application to output matching stage 4.
Output matching stage 4 includes a choke coil L1, a high frequency bypass capacitor C1, a coupling capacitor C2, and an output matching capacitor C3. High frequency bypass capacitor C1 is connected between power supply terminal B and ground, power supply terminal B is connected to one end of choke coil L1, and the other end of choke L1 is connected to the collector of buffer transistor Q1 and to output terminal P through coupling capacitor C2. The other end of choke coil L1 is also grounded through output matching capacitor C3.
In the VCO as illustrated in FIG. 1, frequency variation varactor diode VD in resonance circuit 21 has its capacitance changed in response to control voltage input to a control terminal C. Resonance circuit 21 provides resonance in response to the capacitances of coupling capacitor C9, and frequency variation varactor diode VD, and resonance inductor L2, and oscillation transistor Q2 oscillates at the resonance frequency. The oscillation output is applied to the base of buffer transistor Q1 through coupling capacitor C5, and the oscillation output is output from the collector of buffer transistor Q1 and output from output terminal P through coupling capacitor C2.
FIG. 2 is a circuit diagram showing another example of a conventional VCO. VCO 10 shown in FIG. 2 as is the case with VCO 1 in FIG. 1 includes an oscillation stage 2, a buffer stage 30, and an output matching stage 4. In the example shown in FIG. 1, bias resistors R1, R2, and R3 are connected between power supply terminal B and ground, divided voltage at the connection point of bias resistors R1 and R2 is applied to the base of buffer transistor Q1 as a bias voltage, and divided voltage at the connection point of bias resistors R2 and R3 is applied to the base of oscillation transistor Q2 as a bias voltage, but in VCO 10 in FIG. 2, separate power supply paths are provided for oscillation stage 2, and for buffer stage 30 and output matching stage 4. More specifically, power supply terminal B is connected to the collector of oscillation transistor Q2, a series circuit of bias resistors R2 and R3 is connected between power supply terminal B and ground, and divided voltage at the connection point of bias resistors R2 and R3 is provided to the base of oscillation transistor Q2 as a bias voltage.
Power supply terminal B is also connected to the collector of buffer transistor Q1 through choke coil L1, a series circuit of bias resistors R5 and R6 is connected between power supply terminal B and ground, and divided voltage at the connection point of bias resistors R5 and R6 is applied to the base of buffer transistor Q1 as a bias voltage. High frequency bypass capacitors C4, C10 and C1 are connected, respectively between power supply lines BL2, BL3 and BL4 connected to power supply terminal B and ground.
Also in the VCO shown in FIG. 2, oscillation stage 2 oscillates at a frequency in response to a control voltage applied to control terminal C, the oscillation output to the emitter of oscillation transistor Q2 is applied to the base of buffer transistor Q1 through high frequency bypass capacitor C5, and the oscillation output is extracted from the collector of buffer transistor Q1 and output to output terminal P through high frequency bypass capacitor C2.
Note that in the VCO shown in FIG. 1, electrical noise superimposed on power supply line BL1 is bypassed to ground by high frequency bypass capacitor C1 which is connected between power supply line BL1 and ground, and that in the VCO shown in FIG. 2, electrical noise is bypassed to the ground side by high frequency bypass capacitors C4, C10 and C1 connected between power supply lines BL2, BL3 and BL4 and ground. However, when VCOs 1 and 10 shown FIGS. 1 and 2 are used for a PLL (Phase Locked Loop), they cannot sufficiently bypass to the ground side electrical noise having a particular frequency such as a signal of a reference frequency for the PLL, and such as a power supply ripple. Therefore noise not bypassed is superimposed on the bases and collectors of buffer transistor Q1 and oscillation transistor Q2, resulting in degradation in the C/N characteristics, S/N characteristics and the like of VCOs 1 and 10.